1. Field of the Invention
The present invention relates to an arithmetical unit for performing accumulating operation.
2. Description of the Prior Art
FIG. 4 shows an existing arithmetical unit including accumulating operation. In FIG. 4, symbol 31 is an adder for performing accumulating operation and 32 is storing means for updating the stored data in response to a clock signal inputted from a clock input terminal 5. Symbol 4 is an input terminal and 6 is an output terminal. The input terminal deals with N bits and the output terminal deals with M bits. Because accumulating operation result is generally larger than input in dynamic range, generality is not lost even for N&lt;M. N-bit input data is supplied to a first input 31a of the adder 31 through the input terminal 4. The output of the storing means 32 is supplied to a second input 31b of the adder 31 as M-bit output data through the output terminal 6. The output of the adder 31 is supplied to an input terminal 32a of the storing means 32.
The operation is described below. Input data is supplied to the adder 31 synchronously with the clock signal inputted from the clock input terminal 5. The result of adding the input data with the output of the storing means 32 by the adder 31 is supplied to the input terminal 32a of the storing means 32 and the contents in the storing means 32 is updated. Thus, whenever new input data is inputted synchronously with the clock signal, accumulating operation is performed by the adder 31 and the accumulating operation result is stored in the storing means 32.
As shown in FIG. 4, the adder 31 occupies a large part in the accumulator. Because the output of the storing means 32 is M bits, the adder 31 should have a constitution allowing addition of M-bit binary numbers. FIG. 5 shows a circuit constitution of an existing M-bit adder. Symbols 33a to 33e are one-bit full adders corresponding to the first bit, second bit, third bit, (m-1)-th bit, and m-th bit (most significant bit) from the least significant bit respectively. The circuit of a full adder is shown, for example, in "A Digital Processor for Decocling Composite TV Signals Using Adoptine FiHering" (IEEE Journal of Solid-State Circuits, vol. sc-21, No. 5 October 1986) by K. Murakami and others. Input data X (expressed by a binary bit string of Xm, Xm-1, . . . , and X1) and input data Y (expressed by a binary bit string of Ym, Ym-1, . . . , and Y1) are supplied to the first and second inputs 331 and 332 respectively constituting the input terminals 31a and 31b of the respectively-corresponding full adders 33a to 33e. The carry output of a full adder corresponding to one lower-order bit is connected to the third input (carry input) 333 of full adders 33b to 33e and the third input 333 of the full adder 33a is connected to a grounding point 34. Moreover, the output of the full adders 33a to 33e serves as the output data 0 (binary bit string of Om, Om-1, . . . , and O1). Therefore, when this is used as the adder of the accumulator shown in FIG. 4, input data (N bits) is inputted to the first input 331 by extending symbols.
However, because the existing arithmetical unit including accumulating operation is constituted as described above, it requires an adder of M bits or the number of bits equivalent to the accumulating operation result. Therefore, the circuit size increases. Moreover, when the adder 31 is constituted as shown in FIG. 5, it is difficult to realize a high operation speed because the worst delay path normally serves as a path for carry propagation from the full adder 33a to the full adder 33e in FIG. 5.
To solve the above problem, the existing arithmetical unit including accumulating operation shown in FIG. 6 is proposed. This example is constituted so as to perform part of accumulating operation with an incrementer having smaller circuit constitution than the adder. In FIG. 6, symbol 1 is an adder, 2a is first storing means, 2b is second storing means, 3 is an incrementer, 4 is an input terminal, 5 is a clock input terminal, and 6a and 6b are first and second output terminals respectively. Similarly to the example in FIG. 4, input data of the accumulator consists of N bits and accumulating operation result consists of M bits (N&lt;M). Input data is supplied to the input 1a of the first adder 1 through the input terminal 4. The adder 1 performs addition of N bits. The output of the first storing means 2a for holding data of N bits (data of low-order predetermined bits) is supplied to the second input 1b. The carry output of the adder 1 is supplied to the first input (carry input) of the incrementer 3 and the second output is supplied to the input of the first storing means 2a. The output of the incrementer 3 is supplied to the second storing means 2b for holding data of (M-N) bits (data of high-order predetermined bits) and the output of the second storing means 2b is supplied to the second input 3b of the incrementer 3. All these inputs and outputs consist of (M-N) bits.
The clock signal is inputted through the clock input terminal 5 and supplied to the first and second storing means 2a and 2b. The data stored in each storing means is updated synchronously with the clock signal. Moreover, the outputs of the first and second storing means 2a and 2b are outputted as the accumulating operation results through the first and second output terminals 6a and 6b. The data length of the both outputs is N bits (low-order predetermined bits) and (M-N) bits (high-order predetermined bits) respectively, and the accumulating operation result of total of M bits is outputted.
The following is the description of the incrementer 3 shown in FIG. 6. FIG. 7 shows a constitution of an (M-N)-bit incrementer. In FIG. 7, I (expressed by a binary bit string of I(m-n), I(m-n-1), . . . , and I1) and O (expressed by a binary bit string of O(m-n), O(m-n-1), . . . , and IO) show input data and output data respectively. Each of input data and output data consists of (M-N) bits. Symbols 7a to 7e show half-adders which correspond to the first bit, second bit, third bit, (M-N-1)-th bit, and (M-N)-th bit (most significant bit) starting with the least significant bit respectively. Input data is supplied to the first inputs 71 of the half-adders 7a to 7e and output data is obtained from the first output (sum output) of the half-adders 7a to 7e . The inputs 72 of the half-adders 7b to 7e are respectively provided with the second output (carry output) of a half-adder corresponding to one lower-order bit and the carry signal is supplied to the second input 72 of the lowest half-adder 7a from the carry input terminal 8. The incrementer circuit in FIG. 7 has the above constitution and performs the following operation.
(1) For carry signal="1"
O=I+1 (Output is obtained by adding 1 to input.) PA1 0=I (Output equals input.)
(2) For carry signal="O"
The case in Item (1) shows incremental operation in which the incrementer operation is controlled by the carry signal. The incrementer customarily includes the second storing means 2b in FIG. 6. However, only the functional (1-adding) section shown in FIG. 7 is hereafter called an incrementer.
Actually, various types of circuits are considered as the half-adder circuit, which can be realized at approx. 2/3 circuit size of a full-adder circuit. For example, though a full adder requires two exclusive-OR circuits and one carry-signal generating circuit, a half adder only requires one exclusive-OR circuit and one carry-signal generating circuit.
The following is the description of the operation of the accumulator shown in FIG. 6. Input data is inputted synchronously with the clock signal inputted from the clock input terminal 5. N-bit input data is added with the output (last-time accumulating operation result of low-order predetermined bits) of the first storing means 2a. The second output of the adder 1 consisting of N-bits is supplied to the input of the first storing means 2a and the output of the adder 1 serving as the carry output of the most significant bit consisting of one bit is fetched to the carry input of the incrementer 3.
The incrementer 3 performs incremental operation in accordance with the carry input based on the accumulating operation result only when the carry signal from the addition result of low-order predetermined bits is "1", that is, carry is executed, and adds "1" to the contents of the second storing means 2b consisting of (M-N) bits (high-order predetermined bits). Unless carry is executed, the incrementer 3 inputs the contents in the second storing means 2b directly to the second storing means 2b again without incrementing the contents.
In accordance with the above operation, accumulating operation is executed whenever new data is inputted, the contents in the first and second storing means 2a and 2b are updated according to the accumulating operation result synchronously with the clock signal, and the accumulating operation result of N bits (low-order predetermined bits) and that of (M-N) bits (high-order predetermined bits) are stored.
That is, the accumulator in FIG. 6 executes the accumulating operation of M bits by incrementing the last-time accumulating operation result of (M-N) bits (high-order predetermined bits) in accordance with carry caused by the accumulating operation result of the input data of N bits (N&lt;M) and the last-time accumulating operation result of N bits (low-order predetermined bits). Thereby, the adder 31 comprising full adders corresponding to M bits shown in FIGS. 4 and 5 is replaced with the adder 1 corresponding to N bits (N&lt;M) and the incrementer 3 comprising half-adders corresponding to (M-N) bits, and the circuit size is decreased. Moreover, the worst delay path serves as the carry propagation path from the lowest full adder of the adder 1 to the highest half-adder of the incrementer 3 and thereby, the operation speed is increased by a value equivalent to decrease of the circuit size.
However, because the existing arithmetical unit including accumulating operation is constituted as described above, the carry propagation path from the lowest full adder of the adder 1 to the highest half-adder of the incrementer 3 serves as the worst delay path. Therefore, it is not easy to further improve the operation speed and there is a problem that, to further improve the operation speed, additional circuits are necessary and thus the circuit size increases.
The present invention is made to solve the above problem and its object is to provide an arithmetical unit including accumulating operation for realizing higher operation speed without increasing the circuit size.